In a “buffered DIMM”, i.e., a DIMM semiconductor memory module on which there is a signal driver/control chip (hub) as is currently planned for DDR2 and DDR3 semiconductor memory modules, two ranks per semiconductor memory module are normally arranged. A rank comprises the quantity of memory chips, which is necessary for occupying the bus width to the controller, which can be a processor, a chip set or also the signal driver/control chip on the semiconductor memory module. The bus width is normally 64 bits (72 bits incl. ECC). With this organization, 16 (or 18 with ECC) chips with 4 bits data width or 8 (or 9 with ECC) chips with 8 bits data width are needed for one rank.
A maximum of two ranks have been used on one DIMM. In the new “buffered DIMMs,” in which the data lines DQ from the controller are also buffered, it makes sense to implement, in deviation from the previous principle, a DIMM including 4 ranks with eight-bit-wide memory chips. Among other things, the required power of the DRAM memory chips plays an important role here. The problem with a DIMM with four ranks is that the load of four individual chips (two chips stacked above one another) occurs per DQ line. Due to this high loading, the planned high speeds, for example, 800 MBit/s, can only be achieved with difficulty.
A×4-based DIMM with two ranks has 18 stacked chips. In each “stacked device”, two 4-bit-wide chips are installed. The lower 18 chips closer to the wiring board form one rank and the outside (upper) 18 chips form a second rank. If this arrangement is expanded to a ×8-based DIMM with 4 ranks, a structure shown diagrammatically in the FIG. 11A is obtained. The structure shown in FIG. 11A is symmetric to a center plane of symmetry A which divides a wiring board 1 into a left- and right-hand half. At equally spaced-apart positions Pos1, Pos2, Pos3, Pos4 to the left and to the right of the center plane of symmetry A, in each case two memory chips 5 are stacked above one another (stacked devices) on the top and bottom O, U of the DIMM module. In addition, there are ECC chips at position O (which are not designated in greater detail). The memory chips of the stacked devices are connected to a signal driver/control chip (hub) 4 via a number of wiring planes of the wiring board 1. Of the lines connecting the memory chips to the hub chip, 8-bit-wide data line runs are shown here, which are connected to the stacked-up memory chips at junction points designated by 3 inside vias 2 which pass through the entire wiring board 1. A first 8-bit-wide data line run leads to a first and second memory chip pair in the position Pos1 next to the plane of symmetry A, in each case on the top O and bottom U of the wiring board 1. In the same manner, a second to fourth 8-bit-wide data line run connects second, third and fourth memory chip pairs in each case on the top and bottom O, U of the wiring board 1 to the hub chip 4. As mentioned, four ranks R1–R4 are provided on this DIMM module. The chips of the first and second rank R1, R2 are arranged on the top O of the wiring board 1 according to FIG. 11A. The chips of the third and fourth rank R3, R4 being arranged on the bottom U of the wiring board 1. Per rank, these are eight memory chips, apart from the two ECC chips and the hub chip 4, which have an 8-bit data organization.
FIG. 11B shows a diagrammatic side view of an extension of the concept shown in FIG. 11A, which provides eight ranks R1–R8 and X8 memory chips with four memory chips stacked in them (the side to the left of the center plane of symmetry A has been omitted for simplification since, of course, it is symmetric to the right-hand side).
In these embodiments according to FIGS. 11A and 11B, the total load is bunched at one point at the end of a DQ line. Due to the high capacitive load, a very poor edge steepness, and thus a small eye opening, is thus achieved. By reducing the impedance of the conductor track, for example by widening it, this effect could be reduced. However, the widening of the conductor tracks needed for this is very difficult or even impossible since they would have to be widened to such an extent that a layout can only be made with difficulty or at higher costs since, for example, additional wiring planes of the wiring board are needed.
A semiconductor memory module has the memory ranks distributed on the top and bottom of the wiring board for thermal reasons. Two memory chips on the front and back of a memory module are in each case connected by a data line run, called a channel. The memory module has four data line runs which in each case connect two memory chips on the front and two memory chips on the back of the memory module.
Also known is to arrange a semiconductor memory modules with approximately equal spacing along a databus.
A semiconductor memory module which, in comparison with conventional semiconductor memory modules, can allow a higher speed with a simple without additional added costs is desirable.